1. Field of the Invention
The present invention relates to an amplifier and an offset regulating circuit.
2. Description of Related Art
A fully differential amplifier has been known. FIG. 7 shows an outline view of the fully differential amplifier.
As shown in FIG. 7, a fully differential amplifier 10 includes two input terminals 11, 12, two output terminals 13, 14, and a reference voltage input terminal 15.
Each of input signals input from the input terminals 11, 12 is amplified and the amplified signals are output from the output terminals 13 and 14.
Here, a reference voltage Vref is input from the reference voltage input terminal 15. Then, output signals VOP, VON from the output terminals 13, 14 are differential mode components, where the magnitudes of the output signals are equal to each other and the sign are opposite to each other with the reference voltage Vref therebetween. In other words, by regulating the reference voltage Vref, the common mode level of the output signals VOP, VON can be shifted regardless of the common mode level of the input signals. For example, the dynamic range of the output signals VOP, VON can be regulated to the range that is optimal to the circuit that is provided in the downstream of the fully differential amplifier 10.
FIG. 8 shows an internal configuration of the fully differential amplifier 10 according to a related art.
The fully differential amplifier 10 includes a signal amplification part 20, a common mode feedback part 30, a first current source 40, and a second current source 50.
The signal amplification part 20 is supplied with a power supply current from the first current source 40, and amplifies the input signals input from the input terminals 11, 12 to output the amplified signals from the output terminals 13, 14. Further, the signal amplification part 20 outputs a common mode voltage VCM between Vop and Von.
The common mode feedback part 30 is supplied with an operating current from the second current source 50. Then, the common mode feedback part 30 compares the reference voltage Vref with the common mode voltage VCM, and feeds back the comparing result as VREG to the first current source 40 which is the current source of the signal amplification part 20.
As such, the common mode voltage VCM is controlled to match the reference voltage Vref by the common mode feedback part 30.
For example, when the common mode voltage VCM is smaller than the reference voltage Vref, the signal VREG is fed back to the first current source 40 so that larger current flows in the signal amplification part 20.
Further, when the common mode voltage VCM is larger than the reference voltage Vref, the signal VREG is fed back to the first current source 40 so that smaller current flows in the signal amplification part 20.
By employing such a configuration, the common mode voltage VCM of the output voltage signals VOP, VON matches the reference voltage Vref, and the output of the differential mode with a center of the reference voltage Vref can be obtained.
For example, Japanese Unexamined Patent Application Publication No. 2007-134940 discloses the configuration to feed back the output of the common mode feedback part 30 to the current source (first current source 40) of the signal amplification part 20.